Clock Divider Lvds

1:5 Differential-to-LVDS Zero Delay ICS8745B Clock Generator
The ICS8745B is a highly versatile 1:5 LVDS Clock Generator and a member of the HiPerClockS™ family of High Performance Clock Solutions from IDT. The Reference Divider, Feedback Divider and Output Divider are each programmable, … View Doc

1 Precision Edge® Micrel, Inc. SY89876L M9999-082407 or (408) 955-1690 DESCRIPTION Integrated programmable clock divider and 1:2 … Read Document

FemtoClock NG Crystal-to-3.3V, 2.5V IDT8T49N008I LVPECL/LVDS
Sets the PLL input clock divider. The divider value has the range of 1, 2, 4 and 5. See Table 3F. 2.5V LVPECL/LVDS CLOCK GENERATOR Revision History Sheet Rev Table Page Description of Change Date A 1 Pin Assignment – repositioned pin numbers (11-20). 4/18/12 … Read Here

LMK04000 Family Low-Noise Clock Jitter Cleaner With Cascaded …
LVDS Clock Outputs (CLKoutX) Maximum Frequency fCLKout (38) RL = 100 Ω 1080 MHz (R Divider 1) system clock signal from the selected CLKinX and CLKinX* input with the divided (N Divider 1) output of the external VCXO attached to the PLL2 OSCin port. … Fetch Full Source

1:4 Low Additive LVDS Buffer With Divider
LVDS Buffer with Divider DIV CDCLVD1213 SCAS897 – JULY 2010 20-MHz clock to 4 pairs of differential LVDS clock outputs with • Low Output Skew of 20 ps (Max) low additive jitter for clock distribution. The input can either be LVDS, LVPECL, or CML. … Read Here

LVDS Buffer/Divider w/Internal Termination and is a member of the HiPerClockS™ family of high performance clock solutions from IDT. The ICS889875 has a selectable ÷1, ÷2, ÷4, ÷8, ÷16 output dividers. The clock input has internal termination resistors, … Fetch Content

+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer With Clock Recovery
16-bit demultiplexer, clock divider, and LVDS output buffer (Figure 3). The PLL consists of a phase/frequen-cy detector (PFD), a loop filter, and a voltage-controlled oscillator (VCO). The MAX3880 is designed to deliver the best combination of jitter performance and power … View Document

800 MHz Clock Distribution IC, PLL Core, Dividers, Delay …
4 independent 800 MHz/250 MHz LVDS/CMOS clock outputs Additive output jitter 275 fs rms Fine delay adjust on 2 outputs, 6-bit delay words N DIVIDER DISTRIBUTION REF SYNCB, RESETB PDB CLK1B CLK1 FUNCTION REFINB REFIN PLL SE TINGS AD9510 PROGRAMMABLE DIVIDERS & PHASE ADJUST … Retrieve Here

AD9511 1.2 GHz Clock Distribution IC, PLL Core, Dividers
Each output has a programmable divider that may be bypassed or set to divide by any integer up to 32. LVDS CLOCK OUTPUTS Termination = 100 Ω differential; default OUT3, OUT4; Differential Output level 40h (41h)<2:1> = 01b 3.5 mA … Fetch This Document

NB6N239S 3.3 V, 3.0 GHz Any LVDS OUT – Semiconductor And …
LVDS OUT ÷1/2/4/8, ÷2/4/8/16 Clock Divider Description The NB6N239S is a high−speed, low skew clock divider with two divider circuits, each having selectable clock divide ratios; 1/2/4/8 and 2/4/8/16. Both divider circuits drive LVDS compatible outputs. … Visit Document

AD9513 800 MHz Clock Distribution IC, Dividers, Delay Adjust …
Divider (Divide = 2 to Divide = 1) 15 30 45 mW For each divider. No clock. LVDS Output 20 50 85 mW No clock. CMOS Output (Static) 30 40 50 mW No clock. CMOS Output (@ 62.5 MHz) 65 110 155 mW Single-ended. At 62.5 MHz out with 5 pF load. CMOS Output (@ 125 … Fetch Doc

Single Chip RX And DPD Solution Featuring ADC: HMCAD1520 PLL …
Internal 1X to 8X Clock Divider LVDS output Full robustness inn RSDS (Low Current) Mode Ultra Low Power Dissipation Dynamic power vs sample rate scaling Coarse & Fine Gain Control 48 Pin QFN Package [1] Excluding Interleaving Spurs … Access Content

Output Divider Control for the feedback output pair, FBOUT/nFBOUT. Determines if the output divider = ÷4 (default), or ÷5. M-LVDS clock to the backplane and also provide two local clocks: one 100MHz LVDS output to an ASIC and one 125MHz output to … Fetch Document

IDT8T49N004I Programmable FemtoClock NG Crystal-to- 3.3V, 2 …
Input Clock Divider P Input Clock Prescaler PS Feedback Divider M Output Divider N VCO Frequency (MHz) 30.72 30.72 1 x2 32 64 1966.08 2.5V LVPECL/LVDS CLOCK GENERATOR Table 3F. Output Divider Nn Coding NOTE: X denotes “don’t care”. Table 3G. … Access Doc

Differential-to-LVDS Buffer/Divider ICS8S89875I W/Internal …
÷8, ÷16 output divider. The clock input has internal termination resistors, ICS8S89875I Data Sheet 1:2 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION Table 1. Pin Descriptions NOTE: Pullup refers to internal input resistors. … View Document

NB7V33M – 1.8V / 2.5V, 10GHz /4 Clock Divider With CML Outputs
1.8V / 2.5V, 10GHz ÷4 Clock Divider with CML Outputs CML and LVDS logic levels. The NB7V33M produces a ÷4 output copy of a n input Clock operating up to 10 GHz with minimal jitter. The Reset pin is asserted on the rising edge. … View Full Source

Dual Clock Divider Buffer
CLKin1 input clock divider results in 250 ps coarse tuning steps. The coarse (digital) delay value takes effect on the clock outputs after a SYNC event. CLKout1_TYPE 1 LVDS Individual clock output format. Select from R1 7:9 [3] CLKout2_TYPE 1 LVDS LVDS/LVPECL. R1 10:12 [3] … Fetch Content

AD9522-1 12 LVDS/24 CMOS Output Clock Generator With …
12 lvds/24 cmos output clock generator with integrated 2.4 ghz vco ad9522-1 rev. 0 clock doubler r divider status programmable r delay reference switchover ref_sel vs gnd rset cprset vcp distribution reference refmon cp status ld p, p + 1 prescaler a/b … View Doc